The present invention relates to a surge current prevention circuit and to a DC power supply using a surge current prevention circuit.
When the voltage of a DC power supply is supplied to a capacitive load including a capacitor, the rapid rise in the voltage when the power is switched ON produces surge current, which is a large current that flows to the capacitor. A fuse is provided to prevent the surge current from damaging the device. When a fuse with a high rating is selected so that the fuse does not frequently break, it may not be capable of responding to abnormal currents. To eliminate this problem, research has been carried out in relationship with surge current prevention circuits that restrict surge currents (rush current) (for example, Japanese Laid-Open Patent Publication No. 5-276657). FIG. 2 shows a circuit described in the publication that is configured in correspondence with the present invention. In the surge current prevention circuit shown in FIG. 2, a capacitive load L is connected to an external DC power supply PS by a power switch SW. The power switch SW comprises a P-channel MOS type transistor. A time constant circuit, which comprises a resistor and capacitor, and a power supply switch transistor, which receives a control signal, are connected to the gate terminal of the power switch SW.
When a predetermined DC voltage is supplied from the external power supply PS to the load L, the power source switch transistor is turned ON. This shifts the transistor of the power switch SW to an ON state. In this case, the voltage supplied to the gate of the power switch SW is determined by the time constant circuit. Accordingly, the current supplied to the capacitive load L is controlled by the transient characteristic of the time constant circuit. Therefore, current does not flow the instant the power supply switch transistor goes ON. Since the power switch SW is gradually turned ON, surge current is not produced.
Research has also been conducted in relationship with DC power supply devices configured so as to restrict surge current with high impedance when the power source is turned ON, and using low impedance during normal functioning so that the operation of the DC power supply circuit and the protective function of the fuse are not affected (for example, refer to Japanese Laid-Open Patent Publication No. 8-272464). FIG. 3 shows a circuit described in the publication that is configured in correspondence with the present invention. This technique uses a comparison circuit. The comparison circuit includes divisional transistors, which respectively detect potentials at the source terminal and the drain terminal of the power switch SW, and a comparator, which detects the difference between the two potentials. In this configuration, the output of the comparator is left open from when the power source is turned ON to when the load L is sufficiently charged so that the power switch SW is not conductive. In this state, the external power supply PS supplies the load L with current, which is restricted by a resistor connected in parallel to the transistor of the power switch. When the potential at the drain terminal is high enough, the output of the comparator is short-circuited and the power switch SW becomes conductive.
As described above, in Japanese Laid-Open Patent Publication No. 5-276657, the occurrence of surge current is prevented by controlling the gate voltage of the power switch with the time constant circuit. However, surge current changes in accordance with the power supply voltage and load. Therefore, with a fixed time constant circuit, it is difficult to control surge current that changes in accordance with various power supplies and loads. Furthermore, the circuit of Japanese Laid-Open Patent Publication No. 276657 cannot control the timing for turning ON the power switch in various operation applications.
In Japanese Laid-Open Patent Publication No. 8-272464, the occurrence of surge current is prevented by the resistor that is connected in parallel to the transistor of the power switch, and current is supplied with the power switch turned ON during normal operation. However, a further transistor is necessary for an OFF state. This increases the ON resistance. Moreover, when controlling current with resistance, an absolute value of the resistance is required. However, it is often difficult to accurately realize the desired resistance value in a typical semiconductor fabrication process. When a current is restricted by the resistance, charging takes time, and the current may change depending on the power supply or load. Furthermore, when shifting from a current restriction mode to the power switch ON state, surge current may be generated by the shifting.